发明名称 Organic light emitting diode display and method for manufacturing the same
摘要 An organic light emitting diode (OLED) display and a manufacturing method thereof, the OLED display includes: a substrate main body; a polycrystalline silicon layer pattern including a polycrystalline active layer formed on the substrate main body and a first capacitor electrode; a gate insulating layer pattern formed on the polycrystalline silicon layer pattern; a first conductive layer pattern including a gate electrode and a second capacitor electrode that are formed on the gate insulating layer pattern; an interlayer insulating layer pattern formed on the first conductive layer pattern; and a second conductive layer pattern including a source electrode, a drain electrode and a pixel electrode that are formed on the interlayer insulating layer pattern. The gate insulating layer pattern is patterned at a same time with any one of the polycrystalline silicon layer pattern and the first conductive layer pattern.
申请公布号 US8865485(B2) 申请公布日期 2014.10.21
申请号 US201414218088 申请日期 2014.03.18
申请人 Samsung Display Co., Ltd. 发明人 Shin Min-Chul;Huh Jong-Moo;Kim Bong-Ju;Lee Yun-Gyu
分类号 H01L21/00;H01L51/56 主分类号 H01L21/00
代理机构 H.C. Park & Associates, PLC 代理人 H.C. Park & Associates, PLC
主权项 1. A method of manufacturing an organic light emitting diode (OLED) display, comprising: preparing a substrate main body; sequentially layering a polycrystalline silicon layer, a gate insulating layer, a doped amorphous silicon layer, and a first metal layer, on the substrate main body; forming the polycrystalline silicon layer pattern that includes the polycrystalline active layer and the first capacitor electrode; forming a gate insulating layer intermediate formed on the polycrystalline silicon layer pattern; forming a first conductive layer intermediate formed on the gate insulating layer intermediate by patterning the polycrystalline silicon layer, the gate insulating layer, the doped amorphous silicon layer and the first metal layer together; forming an interlayer insulating layer on the first conductive layer intermediate; forming a first conductive layer pattern and an interlayer insulating layer pattern exposing a portion of the gate insulating layer intermediate by patterning the first conductive layer intermediate and the interlayer insulating layer; forming a gate insulating layer pattern exposing a portion of the polycrystalline active layer by etching the gate insulating layer intermediate exposed through the first conductive layer pattern and the interlayer insulating layer pattern; and forming a second conductive layer pattern on the polycrystalline active layer and the interlayer insulating layer pattern.
地址 Youngin KR