发明名称 Sequential analog/digital conversion and multiplication
摘要 An embodiment of an apparatus for performing sequential analog/digital conversion and multiplication generates upon completing the conversion a digital output indicative of an analog input and a digital product equivalent to the product formed by multiplying a digital operand with the digital output indicative of the input. The apparatus is configured to exploit parallelism per conversion iteration such that the time per iteration can be substantially determined by the conversion processing. During each iteration, a converter processes the analog input to determine the manner in which to refine the digital output while a multiplier combines the operand with a previous partial result to generate a speculative partial result and a weighted previous partial result. According to the determination, the converter refines the digital output while the multiplier selects as a partial result output the speculative partial result or the weighted previous partial result. Additional embodiments are shown and described.
申请公布号 US8866662(B1) 申请公布日期 2014.10.21
申请号 US201213656735 申请日期 2012.10.21
申请人 发明人 Naumov Steve
分类号 H03M1/38;H03M1/62;H03M1/16 主分类号 H03M1/38
代理机构 代理人
主权项 1. An apparatus for analog/digital conversion and multiplication, said apparatus comprising: conversion circuitry for converting an analog input to a digital output, said conversion circuitry configured to refine in succession said digital output by processing said analog input, said conversion circuitry completing conversion when said digital output becomes indicative of said analog input; and multiplication circuitry configured to generate a digital product equivalent to the product formed by multiplying a digital operand with said digital output indicative of said analog input, wherein said digital product is determined prior to said digital output becoming indicative of said analog input.
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