Memory arbitration circuitry

摘要

An integrated circuit with memory elements is provided. The memory elements may be single-port memory cells that are used to provide multiport memory functionality. The integrated circuit may include an arbitration circuit operable to receive memory access requests from at least first and second request generators. The arbitration circuit may be configured to operate in a synchronous mode and an asynchronous mode. The arbitration circuit operating in the synchronous mode may perform port selection based on a predetermined logic table. The arbitration circuit operating in the asynchronous mode may execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed.

主权项

1. A dual-port memory having first and second ports comprising:
an array of single-port memory elements; a control circuit that is coupled to the array and that is operable to read data from and write data into the array; a first request generator operable to receive a first memory access request from the first port; a second request generator operable to receive a second memory access request from the second port; and an arbitration circuit coupled to the control circuit and the first and second request generators, wherein the arbitration circuit is operable in a synchronous mode in which the first and second request generators are controlled using first and second clock signals having equal frequencies and is operable to direct the control circuit to fulfill a single one of the first and second memory access requests during each clock period of the first clock signal and during each clock period of the second clock signal.