发明名称 |
Method of making a non-volatile double gate memory cell |
摘要 |
A method of making a non-volatile double-gate memory cell. The gate of the control transistor is formed with a relief of a semiconductor material on a substrate. The control gate of the memory transistor is formed with a sidewall of the relief of a semiconductor material configured to store electrical charge. A first layer is deposited so as to cover the stack of layers. The first layer is etched so as to form a first pattern juxtaposed on the relief. A second layer is formed on the first pattern. The second layer is etched so as to form on the first pattern a second pattern having a substantially plane upper face. |
申请公布号 |
US8865548(B2) |
申请公布日期 |
2014.10.21 |
申请号 |
US201313736524 |
申请日期 |
2013.01.08 |
申请人 |
Commissariat a l'Energie Atomique et aux Energies Alternatives |
发明人 |
Charpin-Nicolle Christelle;Jalaguier Eric |
分类号 |
H01L21/336;H01L29/423;H01L29/78;H01L21/28;H01L29/66;H01L29/792 |
主分类号 |
H01L21/336 |
代理机构 |
Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
代理人 |
Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
主权项 |
1. A method of making a non-volatile double-gate memory cell comprising a control transistor comprising a gate and a memory transistor comprising a control gate adjacent to the gate of the control transistor, wherein the method comprises the steps of:
forming at least partly the gate of the control transistor, comprising obtaining a relief of a semiconductor material on a substrate; forming the control gate of the memory transistor, comprising the steps of: forming on at least one sidewall of the relief of a semiconductor material and at least one part of the substrate of a stack of layers configured to store electrical charges; depositing a first layer of a semiconductor material so as to at least cover the stack of layers; etching of the first layer so as to form a first pattern, juxtaposed on the relief of a semiconductor material of the gate of the control transistor; wherein said forming of the control gate of the memory transistor additionally comprises the following steps of: forming a second layer of a semiconductor material, at least on the first pattern; etching of the second layer so as to form on the first pattern a second pattern having a substantially plane upper face configured to permit defining a contact area on the control gate of the memory transistor. |
地址 |
Paris FR |