发明名称 METHOD FOR FABRICATING A SEMICONDUCTOR MEMORY
摘要 A method for fabricating a semiconductor memory includes the following steps. Active areas are defined in a substrate. An oxide layer is then formed on the active areas. The oxide layer is subjected to a surface treatment. A first polysilicon layer, a buffer layer and a hard mask are deposited. Recessed access devices are formed in an array region of the substrate. After the recessed access devices are formed, the hard mask and the buffer layer are removed to thereby form transistors in a peripheral region. A second polysilicon layer is deposited on the first polysilicon layer. The first and second polysilicon layers are then etched into a gate structure.
申请公布号 US2014308807(A1) 申请公布日期 2014.10.16
申请号 US201414249357 申请日期 2014.04.10
申请人 INOTERA MEMORIES, INC. 发明人 Hu Yaw-Wen;Chu Ron Fu;Lee Tzung-Han
分类号 H01L21/28 主分类号 H01L21/28
代理机构 代理人
主权项 1. A method for fabricating a semiconductor memory, comprising: providing a semiconductor substrate having a memory array region and a peripheral circuit region thereon; forming active areas in the semiconductor substrate; forming an oxide layer on the active areas, wherein the oxide layer acts as a gate oxide layer in the peripheral circuit region; subjecting the oxide layer to a surface treatment; depositing a first polysilicon layer, a buffer layer, and a hard mask on the oxide layer; fabricating recessed access devices in the memory array region, comprising: forming an opening in the hard mask within the memory array region by using lithographic and etching processes, performing a dry etching process to etch the buffer layer, the first polysilicon layer, the oxide layer, and the semiconductor substrate through the opening to thereby form a trench; forming a gate oxide layer on a surface of the trench; depositing metal into the trench; and filling the trench with a dielectric layer;removing the hard mask and the buffer layer; andfabricating transistors in the peripheral circuit region, comprising:depositing a second polysilicon layer on the first polysilicon layer; andpatterning the first and second polysilicon layers into a gate structure.
地址 Taoyuan TW