3D MEMORY ARRAY

摘要

A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line.

主权项

1. A three-dimensional memory array, comprising:
a plurality of word line layers disposed on a substrate, each of the word line layers having a plurality of word lines and a plurality of gaps arranged alternately along a first direction, the gaps comprising a first group of gaps and a second group of gaps arranged alternately; a first bit line layer, disposed above the word line layers and having a plurality of first bit lines arranged along a second direction, the second direction being perpendicular to the first direction; a first conductive pillar array, extending through the word line layers and electrically connected to the first bit line layer, the first conductive pillar array comprising a plurality of first conductive pillars disposed in the first group of gaps, wherein a first memory element is disposed between a first conductive pillar and a word line of the word line layer adjacent to the first conductive pillar and located to cover a bottom surface of the first conductive pillar; a second bit line layer, disposed above the first bit line layer and having a plurality of second bit lines arranged along the second direction, wherein the first bit lines and the second bit lines are arranged alternately; and a second conductive pillar array, extending through the word line layers and electrically connected to the second bit line layer, the second conductive pillar array comprising a plurality of second conductive pillars disposed in the second group of gaps, wherein a second memory element is disposed between a second conductive pillar and a word line of the word line layer adjacent to the second conductive pillar and located to cover a bottom surface of the second conductive pillar, and the first conductive pillars and the second conductive pillars are in a staggered arrangement.