FIFO Clock and Power Management

摘要

An apparatus and method for saving power when transmitting data across a clock boundary is disclosed. In one embodiment, an apparatus includes a FIFO coupled to receive data from circuitry in a first clock domain and output data to circuitry in a second clock domain. A first control circuit is responsible for writing data into the FIFO. A second control circuit is responsible for reading data from the FIFO. If the amount of data in the FIFO exceeds a first threshold, a power management circuit may place the first control circuit in a low power state. The second control circuit may monitor the amount of data in the FIFO. If the amount of data in the FIFO falls below a second threshold, it may assert an indication to the power management circuit. Thereafter, the power management circuit may cause the first control circuit to exit the low power state.

主权项

1. An apparatus comprising:
a first-in, first-out memory (FIFO) coupled to receive data from circuitry operating according to a first clock signal having a first frequency and further coupled to output data to circuitry operating according to a second clock signal having a second frequency; a first FIFO controller in the first clock domain, wherein the first FIFO controller is configured to cause data to be written into the FIFO; a second FIFO controller in the second clock domain, wherein the second FIFO controller is configured to cause data to be read from the FIFO; and a power management unit, wherein the power management unit is configured to place the first FIFO controller into a low power state responsive to determining that the amount of data in the FIFO exceeds a first threshold, and further configured to wake the first FIFO controller from the low power state responsive to receiving an indication from the second FIFO controller.