| 摘要 |
PROBLEM TO BE SOLVED: To facilitate identification of a bug out of a scenario defined for a circuit.SOLUTION: At rise clock timing t5 of a clock Clk, a value of a register R changes from "3" to "5", and this change is not expected by any assertions A1 and A2. Specifically, at rise clock timing t6 which is one cycle after the rise clock timing t5, the actual value of the register R "5" and an expectation value of the register R_spec "3" do not match with each other, and as the value of the register R has changed out of the assertions A1 and A2, this is detected as an error. Thus, a bug generated in a scenario which is not defined by the assertion A1 and A2 can be detected, so that it is possible to detect a bug even when an assertion do not cover all actions in a verification target circuit. Also, a verifier can ensure that the value of the register R does not change out of the assertion in the verification target circuit by debugging the identified bug. |
