Multi-processor bus and cache interconnection system

摘要

A multi-processor cache and bus interconnection system. A multi-processor is provided a segmented cache and an interconnection system for connecting the processors to the cache segments. An interface unit communicates to external devices using module IDs and timestamps. A buffer protocol includes a retransmission buffer and method.

主权项

1. A method for operating a system, the system comprising:
a data processor, the data processor having at least one arithmetic-logic unit and at least one cache; a bus system connecting the data processor to a receiver, the receiver comprising at least one of an external memory and an external peripheral;
the bus system comprising a buffer memory; the buffer memory having three associated pointers:
i. a first pointer to point to the buffer from which data is output from the buffer;ii. a second pointer to point the buffer location to which data is input to the buffer; andiii. a third pointer to store the value of the first pointer at the start of a data transfer;wherein the method of operations comprises:
i. storing transfer data in the buffer memory;ii. transmitting data to the receiver;iii. the receiver transmitting information as to whether a data transfer was successful or has failed;iv. if the transfer has failed, repeating the transfer of data from the buffer position indicated by the third associated pointer by resetting the first pointer with the value of the third.