发明名称 TWO-WIRE TYPE INSPECTION CIRCUIT MOUNTED FPGA
摘要 PROBLEM TO BE SOLVED: To elicit a software error by devising write-in contents to a look-up table (LUT) 34.SOLUTION: When a two-wire type inspection circuit (15) is mounted by writing in on a look-up table (LUT) type FPGA (30) comprising a large number of four-input one-output LUTs 34, logical elements 21, 22, 23 are distributed one by one and mounted by writing in on each of LUTs 34a, 34b, 34c, and at a place, where none of two inputs of the mounted logical elements are input, among four inputs of each LUT 34a, 34b, 34c, a fixed value "0" is input, and thereby read out places are made to be limited to four places (▵) of which the addresses correspond to any of all bit patterns of two inputs of the mounted logical elements for any of the LUTs 34a, 34b, 34c. This elicits a software error in a form of non-correspondence of a comparison check result.
申请公布号 JP2014197754(A) 申请公布日期 2014.10.16
申请号 JP20130071871 申请日期 2013.03.29
申请人 DAIDO SIGNAL CO LTD 发明人 TERADA TAKAYUKI;WATANABE SHIKO;ISHIKAWA SUSUMU
分类号 H03K19/173 主分类号 H03K19/173
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