| 摘要 |
An SRAM or FLASH memory unit 10 comprised of memory cells 20 grouped into memory cell groups 30 each group having one or more local bit lines (31, 32) operatively connected to each of the memory cells within the group. The local bit lines of the memory cell groups are connected to a switching circuit 33, and the switching circuit is configured to cause a capacitance element 34 to be connected to one of the one or more global bit lines 11, 12 in dependence upon the states of the one or more local bit lines of the memory cell group. A sensing circuit is configured to determine the data value stored in a memory cell in dependence upon the states of the one or more global bit lines. The capacitance element may be a capacitor 34a (16b figure 13) or may be provided by one or more local bit lines of further memory cell groups or an adjacent group (figure 12). The local bit line may be operatively connected to a respective global line by means of a switch 35,36 activated by a switch control signal. The extra (capacitive) switching circuit 33 may comprise (for each global bit line) a first PMOS transistor (33a,33c figure 10) and a second PMOS transistor (33b, 33d) the gate of the first transistor connected to the local bit line and the gate of the second transistor connected to the switch control line. A local bit line pre-charge circuit 15a is also included (figure 12). Includes a method of operation. |
