发明名称
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor wafer which downsizes a semiconductor chip. SOLUTION: The semiconductor wafer includes a semiconductor substrate 21 which has a plurality of chip forming regions 23 on each of which a semiconductor device 24 is formed, and inter-layer insulation films 50-80, on which an inspection pad 41a and a signal pad 41b are formed, on one surface. The signal pad 41b is arranged at a location facing the semiconductor device 24 and electrically connected with the semiconductor device 24 through vias 52c-82c formed inside the inter-layer insulation films 50-80. An inspection wire 61c is provided at a position between the signal pad 41b and the semiconductor device 24 inside the inter-layer insulation films 50-80, and the inspection pad 41a and the signal pad 41b are electrically connected through the inspection wire 61c. COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP5604992(B2) 申请公布日期 2014.10.15
申请号 JP20100125630 申请日期 2010.06.01
申请人 发明人
分类号 H01L21/66 主分类号 H01L21/66
代理机构 代理人
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