Apparatus for at-speed testing, in inter-domain mode, of a multi-clock-domain digital integrated circuit according to BIST or SCAN techniques

摘要

An embodiment is directed to extended test coverage of complex multi-clock-domain integrated circuits without forgoing a structured and repeatable standard approach, thus avoiding custom solutions and freeing the designer to implement his RTL code, respecting only generally few mandatory rules identified by the DFT engineer. Such an embodiment is achieved by introducing in the test circuit an embodiment of an additional functional logic circuit block, named “inter-domain on chip clock controller” (icOCC), interfaced with every suitably adapted clock-gating circuit (OCC), of the different clock domains. The icOCC actuates synchronization among the different OCCs that source the test clock signals coming from an external ATE or ATPG tool and from internal at-speed test clock generators to the respective circuitries of the distinct clock domains. Scan structures like the OCCs, scan chain, etc., may be instantiated at gate pre-scan level, with low impact onto the functional RTL code written by the designer.

主权项

1. An integrated circuit, comprising:
a first clock source configured to provide a first clock signal having a first frequency; a second clock source configured to provide a second clock signal having a second frequency; and a control circuit configured, during a test mode, to cause the first clock source to provide an initial edge of the first clock signal after a reference time such that the initial edge corresponds to an initial edge of the second clock signal after the reference time.