Tamper-resistant memory integrated circuit and encryption circuit using same

摘要

An integrated memory circuit applies to an S-box of a cryptographic circuit. The integrated memory circuit includes a row decoder, a column decoder, and a sense amplifier composed of a domino-RSL circuit, wherein data reading and data writing from/to memory cells of a memory cell array are performed via two complementary bit lines, and the transition probability of a signal line is equalized by input of random-number data supplied from a random-number generating circuit using an arbiter circuit.

主权项

1. An integrated memory circuit, comprising:
a memory cell array; a row decoder; a column decoder; a sense amplifier; and an input/output driver, the integrated memory circuit further comprising two complementary bit lines for performing data reading from and data writing to memory cells of the memory cell array; and an input control line to which random-number data and address data are supplied, wherein: a result of an exclusive-OR operation of the random-number data and address data is supplied to the row decoder and the column decoder as the address data, a result of an exclusive-OR operation of the random-number data and the address data is converted into a word decode signal in the row decoder, a result of an exclusive-OR operation of the random-number data and the address data is converted into a column decode signal in the column decoder, the memory cell array is accessed by the word decode signal and the column decode signal, and data of the memory cell thus accessed is transmitted to the sense amplifier via the two complementary bit lines, and the sense amplifier carries out an exclusive-OR operation of the data of the memory cell thus accessed and the random-number data and the input/output driver outputs the operation result as data of the memory cell.