Hierarchical feature extraction for electrical interaction calculations

摘要

A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

主权项

1. A computer-implemented method for performing parasitic extraction for an integrated circuit layout representing an integrated circuit, comprising:
creating within a computer memory, a hierarchical database comprising cells that represent the integrated circuit layout, one or more of the cells comprising data defining one or more polygons that define size and location of circuit components in the integrated circuit layout; computing parasitic extraction values for the one or more of the cells in the integrated circuit layout, wherein the parasitic extraction values for the one or more of the cells include both resistances and capacitances; and based on the parasitic extraction values for the one or more of the cells, computing parasitic extraction values for interacting ones of the cells to represent electrical behavior between one or more of the circuit components of the integrated circuit layout.