Symmetric blocking transient voltage suppressor (TVS) using bipolar NPN and PNP transistor base snatch

摘要

A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.

主权项

1. A method of manufacturing a symmetrical blocking transient voltage suppressing (TVS) circuit comprising:
implanting a first and second wells of a first conductivity type in an epitaxial layer of a second conductivity type constituting a third well of the second conductivity type between the first and second wells supported on a substrate of the second conductivity type; forming a first and second gates padded with a gate insulation layer on a top of the third well laterally opposite from the first and second doped wells; and applying an implant mask to carry out a source and drain implant with dopant of the first conductivity type for forming a source region and a drain region on two opposite sides of the first and second gates to form two transistors with interconnecting source regions.