发明名称 |
Fault tolerant parallel receiver interface with receiver redundancy |
摘要 |
A communications parallel bus receiver interface having N+1 data lines and method of operation. The parallel bus interface employs receiver redundancy at the bus level such that there are N+1 receiver devices. One of the N+1 data signals comprising a spare data signal when a failure occurs in a corresponding channel transmitting one of N parallel data signals. An input switching network is configured to receive and couple N+1 parallel data signals along respective paths to corresponding parallel-configured bit receiver devices, and adapted to couple one received data signal to two or three adjacent bit receivers. A calibration device calibrates one of the two or three adjacent bit receivers, and a qualification device qualifies data decisions made during calibration processes performed by the calibration device. The method cycles through N+1 receivers for periodic recalibration of each receiver (one at a time) while N+1 inputs are processed continuously and uninterrupted. |
申请公布号 |
US8861513(B2) |
申请公布日期 |
2014.10.14 |
申请号 |
US201313736353 |
申请日期 |
2013.01.08 |
申请人 |
International Business Machines Corporation |
发明人 |
Dickson Timothy O.;Dreps Daniel M.;Ferraiolo Frank D. |
分类号 |
H04L12/50;H04L12/28;H04L12/66;H04J3/02;H04L27/00;H04L12/24;G06F13/00;H04L12/933 |
主分类号 |
H04L12/50 |
代理机构 |
Scully, Scott, Murphy & Presser, P.C. |
代理人 |
Scully, Scott, Murphy & Presser, P.C. ;Dougherty, Esq. Anne V. |
主权项 |
1. A method for calibrating receivers of a parallel I/O bus receiver interface, said method comprising:
receiving N+1 parallel data signals along respective paths, one of said N+1 parallel data signals comprising a spare data signal; coupling received N parallel data signals along respective paths to corresponding N receiver devices of N+1 parallel-configured bit receiver devices, and coupling a remaining one received parallel data signal to two adjacent bit receivers or two adjacent bit receivers of two or three adjacent parallel bit receivers; calibrating, using a calibration logic device, one of said two adjacent bit receiver devices during a calibration cycle; qualifying, using a qualification logic device, data decisions made during calibration processes performed by the calibration logic device, wherein a same data signal being used for calibrating a receiver during said calibration cycle is provided to the adjacent receiver of either said two adjacent or said three adjacent bit receivers; and configuring an output switching network to route an output of the bit receiver being calibrated to said calibration logic block, and simultaneously route outputs of the remaining N bit receivers of the N+1 parallel-configured receivers as N-bit wide parallel data signal outputs, wherein one output of an adjacent receiver receiving said same data signals during said calibration cycle is simultaneously routed to said qualification logic block. |
地址 |
Armonk NY US |