Characterization based buffering and sizing for system performance optimization

摘要

A method for timing optimization of an integrated circuit design using a timing optimization system comprising loading an original delay value and an original gate configuration net-list for an original gate from a results database. A near optimum gate configuration is identified using near optimum gate configuration information stored in a delay characterization database for the original gate. A near optimum delay value and a near optimum gate configuration net-list of a near optimum gate configuration are loaded. A timing optimized gate configuration is provided from running an incremental static timing analysis of the near optimum gate configuration.

主权项

1. A method for timing optimization of an integrated circuit design implemented using an electronic design automation processing system having at least a processor and a database storage, the method comprising:
loading an original delay value and an original gate configuration net-list for an original gate from a results database; identifying an ideal gate configuration using gate configuration information stored in a delay characterization database for the original gate; loading an ideal delay value and an ideal gate configuration net-list of the ideal gate configuration; and producing a timing optimized gate configuration from running an incremental static timing analysis on the loaded gate configuration.