发明名称 |
Decision feedback equalizer |
摘要 |
A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit. |
申请公布号 |
US8862951(B2) |
申请公布日期 |
2014.10.14 |
申请号 |
US201213528877 |
申请日期 |
2012.06.21 |
申请人 |
Taiwan Semiconductor Manufacturing Co., Ltd. |
发明人 |
Huang Ming-Chieh;Chern Chan-Hong;Chung Tao Wen;Swei Yuwen;Lin Chih-Chang;Huang Tsung-Ching |
分类号 |
G06F11/00;H04L27/01 |
主分类号 |
G06F11/00 |
代理机构 |
Duane Morris LLP |
代理人 |
Duane Morris LLP |
主权项 |
1. A circuit, comprising:
a first summation circuit configured to receive an input data signal and a feedback signal including a previous data bit, the first summation circuit configured to combine the input data signal and the feedback signal to generate a conditioned input data signal that is output to a clock and data recovery circuit that is coupled to an output of the first summation circuit; a first flip-flop coupled to the output of the first summation circuit, the first flip-flop configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit; and a second flip-flop coupled to the output of the first summation circuit, the second flip-flop configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit, wherein the first flip-flop and the second flip-flop are configured output respective signals to additional circuitry that receives the signals from the first flip-flop and the second flip-flop and outputs the feedback signal. |
地址 |
Hsin-Chu TW |