Nonvolatile semiconductor memory device and method of manufacturing the same

摘要

According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other.

主权项

1. A nonvolatile semiconductor memory device, comprising:
a semiconductor substrate; a first semiconductor layer extending in a first direction parallel to an upper surface of the semiconductor substrate; a second semiconductor layer extending in the first direction, the second semiconductor layer disposed above the first semiconductor layer; a third semiconductor layer extending in the first direction; a fourth semiconductor layer extending in the first direction, the fourth semiconductor layer disposed above the third semiconductor layer; a first portion electrically connected to one end of the first semiconductor layer and one end of the second semiconductor layer; a second portion electrically connected to one end of the third semiconductor layer and one end of the fourth semiconductor layer; a third portion including a fifth semiconductor layer, a sixth semiconductor layer, and an insulating layer therebetween, the fifth semiconductor layer being connected between the other ends of the first and third semiconductor layers, the sixth semiconductor layer being connected between the other ends of the second and fourth semiconductor layers; a first control gate electrode disposed above side surfaces of the first and second semiconductor layers through a first memory area; a second control gate electrode disposed above side surfaces of the third and fourth semiconductor layers through a second memory area; a first select gate electrode disposed between the first portion and the first control gate electrode; a second select gate electrode disposed between the second portion and the second control gate electrode; a third select gate electrode disposed between the third portion and the first control gate electrode; and a fourth select gate electrode disposed between the third portion and the second control gate electrode.