| 摘要 |
Integrated circuits with wireless communications circuitry having peak cancelling circuitry operable to perform crest factor reduction is provided. The peak cancelling circuitry may include a peak detection circuit, a delay circuit, and peak cancellation pulse generation circuitry. The peak cancellation pulse generation circuitry may include multiple pulse generation blocks coupled in a cascade configuration. Each pulse generation block may include a counter for providing memory address signals, a register for latching peak scaling factor information, a pulse memory block for storing a respective sub-pulse, and a multiplier for scaling the stored sub-pulse by the latched peak scaling factor. The pulse memory block may be implemented using single-port memory or dual-port memory. In other suitable arrangements, the peak cancellation pulse generation circuitry may include an allocator circuit and a crossbar switch for selectively coupling the counters and registers to respective pulse memory blocks and multipliers. |
