Wiring-optimal method to route high performance clock nets satisfying electrical and reliability constraints

摘要

High performance clock distributions and similar wiring networks require improvements in reliability and performance. This is especially true when hierarchical wiring with different metal thicknesses is employed and when a smaller number of large, higher-power buffers are used to reduce timing variability. Routing of critical nets improves robustness, reliability, and resistance while minimizing track and power usage. The method further optimizes the use of multiple physical pins on buffers to achieve desired electrical criteria. This involves optimal selection of additional routing beyond what is needed to satisfy simple connectivity. The routing involves an iterative process to select and evaluate additional possible routes on multiple layers. Each iteration involves extraction and simulation or estimation, and additional routes are added until the desired electrical criteria are met.

主权项

1. A method of routing nets in an integrated circuit comprising:
creating, by a computer, at least one robust output pin structure comprising multiple wire segments on one or more metal layers; using said multiple wire segments for routing to one or more receiving buffers of said nets; and adding wiring connections between output pin shapes of one or more driving buffers of said nets and said at least one robust output pin structure determined by requirements of electrical and reliability metrics, said robust output pin structure located between said one or more driving buffers and said one or more receiving buffers, wherein said at least one robust output pin structure is placed substantially adjacent to said output pin shapes of said one or more driving buffers for adding said wiring connections iteratively based on satisfying said electrical and reliability metrics.