Storage cell bridge screen technique

摘要

A semiconductor memory includes a circuit block that is configured to receive a test mode command, a first sense amplifier that is coupled to sense and amplify a state of a first memory cell when enabled, and a second sense amplifier that is coupled to sense and amplify a state of a second memory cell when enabled. In an active cycle, the circuit block generates one or more control signals in response to the test mode command that cause the second sense amplifier to be enabled a predetermined amount of time after the first sense amplifier is enabled.

主权项

1. A method for detecting a bridge between two memory cells in a memory array having a plurality of memory cells coupled to wordlines and bitlines, the method comprising:
receiving a test mode command; and in response to an active command, enabling a first sense amplifier and a second sense amplifier for respectively sensing a state of a first memory cell and a second memory cell; wherein the first and second memory cells are adjacent one another, and the test mode command causes the second sense amplifier to be enabled a predetermined amount of time after the first sense amplifier is enabled.