发明名称 Programmable graphics processor for multithreaded execution of programs
摘要 A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.
申请公布号 US8860737(B2) 申请公布日期 2014.10.14
申请号 US200611458633 申请日期 2006.07.19
申请人 NVIDIA Corporation 发明人 Lindholm John Erik;Coon Brett W.;Oberman Stuart F.;Siu Ming Y.;Gerlach Matthew P.
分类号 G06F15/16;G06F15/80;G06T1/20;G06T15/00;G06F12/08;G06T15/10 主分类号 G06F15/16
代理机构 Patterson & Sheridan, LLP 代理人 Patterson & Sheridan, LLP
主权项 1. A processing unit comprising: a first input section for receiving pixel data; a second input section for receiving vertex data; a first execution pipeline coupled to the first input section and the second input section, wherein the first execution pipeline includes a plurality of parallel data execution paths through which a group of pixel data or vertex data is processed in parallel; a first output section coupled to the first execution pipeline for storing pixel data processed by the first execution pipeline; a second output section coupled to the first execution pipeline for storing vertex data processed by the first execution pipeline, and a second execution pipeline coupled to the first input section, the second input section, the first output section, and the second output section.
地址 Santa Clara CA US