发明名称 Direct mm-wave m-ary quadrature amplitude modulation (QAM) modulator operating in saturated power mode
摘要 In one embodiment, a circuit comprises a first pair of elements, a second pair of elements, a combiner, and a signal output. Each element in the first and second pair of elements comprises an amplitude-control input for receiving an amplitude-control bit, a phase-control input for receiving a phase-control bit, a signal input for receiving an input signal, a modulator for producing an output signal based on the amplitude-control bit, the phase-control bit, and the input signal, and an signal output for transmitting the output signal to the combiner. The combiner combines the two output signals from the first and second pair of elements to produce an output signal for the circuit to be transmitted by the signal output of the circuit.
申请公布号 US8861627(B2) 申请公布日期 2014.10.14
申请号 US200912503708 申请日期 2009.07.15
申请人 Fujitsu Limited 发明人 Voinigescu Sorin P.;Tomkins Alexander;Wiklund Magnus O.;Walker William Warren
分类号 H04L5/12;H04B15/00;H01Q3/00;H04L27/36;H03D7/14;H03C1/36;H03D7/16 主分类号 H04L5/12
代理机构 Baker Botts L.L.P. 代理人 Baker Botts L.L.P.
主权项 1. A method comprising: receiving an amplitude-control bit, a phase-control bit, and an input signal; modulating the amplitude of the input signal based on the amplitude-control bit and modulating the phase of the input signal based on the phase-control bit to produce an output signal, the output signal comprising an amplitude and a phase, there being three potential states for the output signal, the amplitude representing binary 0 in a first one of the three potential states, the amplitude representing binary 1 and the phase representing binary 0 in a second one of the three potential states, the amplitude representing binary 1 and the phase representing binary 1 in a third one of the three potential states, wherein the amplitude of the output signal represents binary 0 if the amplitude-control bit is binary 0, and the phase-control bit is binary 0 or binary 1, and wherein the amplitude of the output signal represents binary 1 and the phase of the output signal represents binary 0 if the amplitude-control bit is binary 1, and the phase-control bit is binary 0; and transmitting the output signal.
地址 Kawasaki-shi JP