Techniques for providing a direct injection semiconductor memory device

摘要

Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.

主权项

1. A method for biasing a direct injection semiconductor memory device comprising the steps of:
applying a first voltage potential to a first N-doped region of the device via a bit line; applying a second voltage potential to a second N-doped region of the device via a source line; applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region of the device that is electrically floating and disposed between the first N-doped region and the second N-doped region, wherein the first N-doped region, the body region, and the second N-doped region form a bipolar transistor; and applying a fourth voltage potential to a P-type substrate of the device via a carrier injection line, wherein the second N-doped region is formed directly on the P-type substrate.