发明名称 Edge rate control gate driver for switching power converters
摘要 This document discusses, among other things, apparatus and methods for an edge rate driver for a power converter switch. In an example, the driver can include an input node configured to receive a pulse width modulated signal, a first switch configured to couple a control node of the power converter switch to a supply voltage during a first state, a second switch configured to couple the control node of the power converter switch to a reference voltage during a second state, and a first current source configured to supply charge current to the first switch when the power converter switch transitions from the second state to the first state, the charge current configured to charge a parasitic capacitance of the power converter switch.
申请公布号 US8860398(B2) 申请公布日期 2014.10.14
申请号 US201113294558 申请日期 2011.11.11
申请人 Fairchild Semiconductor Corporation 发明人 Mulligan Michael David;Dhuyvetter Timothy Alan
分类号 G05F1/16;H02M1/44;H03K3/00;H02M3/155;H03K17/16 主分类号 G05F1/16
代理机构 Schwegman, Lundberg & Woessner, P.A. 代理人 Schwegman, Lundberg & Woessner, P.A.
主权项 1. An edge rate driver for a power converter switch, the edge rate driver comprising: an input node configured to receive a pulse width modulated signal; a first switch configured to couple a control node of the power converter switch to a supply voltage during a first state; a second switch configured to couple the control node of the power converter switch to a reference voltage during a second state; a first current source configured to supply charge current to the first switch when the power converter switch transitions from the second state to the first state, the charge current configured to charge a parasitic capacitance of the power converter switch; a second current source configured to provide discharge current for the second switch when the power converter switch transitions from the first state to the second state, the discharge current configured to discharge the parasitic capacitance of the power converter switch; and a feedback circuit configured to receive a voltage from an output node of the power converter switch and to modulate a transition of the control node of the power converter switch, the feedback circuit configured to hard switch the control node of the power converter switch; wherein the feedback circuit includes: a first hard switch transistor configured to couple the control node of the power converter switch to the supply voltage during the first state; a second hard switch transistor configured to couple the control node of the power converter switch to the reference voltage during the second state; and a hysteretic comparator coupled to a control node of the first hard switch transistor and to a control node of the second hard switch transistor, the hysteretic comparator configured to receive the voltage from the output node of the power converter switch to control the control node of the first hard switch transistor and the control node of the second hard switch transistor.
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