发明名称 Spacer assisted pitch division lithography
摘要 Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern.
申请公布号 US8860184(B2) 申请公布日期 2014.10.14
申请号 US201113976077 申请日期 2011.12.29
申请人 Intel Corporation 发明人 Sivakumar Swaminathan;Tan Elliot N.
分类号 H01L29/06;H01L23/58;H01L21/44;H01L21/02 主分类号 H01L29/06
代理机构 Finch & Maloney PLLC 代理人 Finch & Maloney PLLC
主权项 1. A method for fabricating an integrated circuit, comprising: providing a variable pitch backbone pattern on a substrate, the pattern having two or more line widths and two or more space widths; depositing a conformal layer of spacer material on the pattern and substrate, wherein the conformal layer has a thickness of 1×, and at least one of the space widths of the pattern is 2× or less and is filled with the spacer material; and removing excess spacer material so as to reveal a top surface of the backbone pattern and to reveal a top surface of the substrate below space widths of the pattern that are greater than 2×, wherein spacer material having a thickness of 1× remains on sidewalls of the pattern, and space widths of the pattern that are 2× or less remain at least partially filled with the spacer material.
地址 Santa Clara CA US