Successive-approximation-register analog-to-digital converter for programmably amplifying amplitude of input signal and method thereof

摘要

Disclosed are a successive-approximation-register (SAR) analog-to-digital converter (ADC) for programmably amplifying an amplitude of an input signal and a method thereof. During a sampling phase, a bottom plate of at least one capacitor in a capacitor array is connected electrically to an input signal, so that the capacitor array samples and amplifies the input signal, so as to lower a required sampling capacitor or reduce noise generation.

主权项

1. A successive-approximation-register (SAR) analog-to-digital converter (ADC) for programmably amplifying amplitude of an input signal, comprising:
a first node, for receiving one of a differential input signal; a second node, for receiving the other one of the differential input signal; a third node, for receiving a positive reference voltage; a fourth node, for receiving an negative reference voltage; a fifth node, for receiving a common-mode voltage; a comparator, having a first input terminal, a second input terminal and an output terminal; an SAR control circuit, coupled to the output terminal to generate a first control signal, a second control signal and a digital signal according to an output of the comparator; a selection module, comprising:
a plurality of first switching units, controlled by the first control signal;a plurality of second switching units, controlled by the second control signal;a first switch, coupled between the first input terminal and the first node; anda second switch, coupled between the second input terminal and the second node; and a capacitor module, comprising:
a plurality of first capacitors, respectively corresponding to the first switching units, each coupled between the first input terminal and the corresponding first switching unit, wherein each of the first capacitors is coupled to the third node, the fourth node and the fifth node through the corresponding first switching unit, and at least one of the first capacitors is further coupled to the second node through the corresponding first switching unit; anda plurality of second capacitors, respectively corresponding to the second switching units, each coupled between the second input terminal and the corresponding second switching unit, wherein each of the second capacitors is coupled to the third node, the fourth node and the fifth node through the corresponding second switching unit.