发明名称 Liquid crystal display device and electronic device
摘要 To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.
申请公布号 US8860462(B2) 申请公布日期 2014.10.14
申请号 US201213675066 申请日期 2012.11.13
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Umezaki Atsushi
分类号 H03K19/0175 主分类号 H03K19/0175
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A semiconductor device comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein a gate of the first transistor is electrically connected to a first wiring, wherein a first terminal of the first transistor is electrically connected to the first wiring, wherein a second terminal of the first transistor is electrically connected to a gate of the third transistor, wherein a first terminal of the second transistor is electrically connected to a second wiring, wherein a second terminal of the second transistor is electrically connected to the gate of the third transistor, wherein a first terminal of the third transistor is electrically connected to the first wiring, wherein a second terminal of the third transistor is electrically connected to a gate of the sixth transistor, wherein a gate of the fourth transistor is electrically connected to a third wiring, wherein a first terminal of the fourth transistor is electrically connected to the second wiring, wherein a second terminal of the fourth transistor is electrically connected to the gate of the sixth transistor, wherein a first terminal of the fifth transistor is electrically connected to the second wiring, wherein a second terminal of the fifth transistor is electrically connected to the gate of the sixth transistor, wherein a first terminal of the sixth transistor is electrically connected to the second wiring, and wherein a second terminal of the sixth transistor is electrically connected to a fourth wiring.
地址 Atsugi-shi, Kanagawa-ken JP