Zero keeper circuit with full design-for-test coverage

摘要

A zero keeper circuit includes a dynamic input PFET connected to a source, an output, and a dynamic input. The circuit also includes a clock input NFET connected to the output, a pull-down node, and a clock input. The circuit also includes a dynamic input NFET connected to the pull-down node, a reference voltage, and the dynamic input. The circuit also includes a feedback PFET and a clock input PFET connected in series between the source and the output. The feedback PFET receives a feedback signal and the clock input PFET receives the clock input. The circuit also includes a feedback NFET connected to the output and the node. The feedback NFET is configured to couple the output to the node based on the feedback signal. The circuit also includes a NOR gate configured to provide the feedback signal based on the output and a bypass input.

主权项

1. A circuit comprising:
a dynamic input PFET connected to a power source and a zero keeper output, wherein the dynamic input PFET is configured to couple the power source to the zero keeper output based on a dynamic input; a clock input NFET connected to the zero keeper output and a pull-down node, wherein the clock input NFET is configured to couple the zero keeper output to the pull-down node based on a clock input; a dynamic input NFET connected to the pull-down node and a reference voltage, wherein the dynamic input NFET is configured to couple the pull-down node to the reference voltage based on the dynamic input; a feedback PFET and a clock input PFET connected in series between the power source and the zero keeper output, wherein the feedback PFET is selectively enabled based on a feedback signal and the clock input PFET is selectively enabled based on the clock input; and a feedback NFET connected to the zero keeper output and the pull-down node, wherein the feedback NFET is configured to couple the zero keeper output to the pull-down node based on the feedback signal; and a NOR gate configured to output the feedback signal based on the zero keeper output and a bypass input.