Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction

摘要

A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

主权项

1. An integrated circuit die comprising:
a device structure formed at a pre-determined location on the die; and one or more dummy structures formed within a pre-defined effective thermal area surrounding a transistor structure and operable for adjusting temperature at the pre-determined location during a thermal anneal process based at least in part on a comparison of an estimated effective temperature at the pre-determined location and a desired temperature at the pre-determined location.