Semiconductor memory device

摘要

A semiconductor memory device according to an embodiment includes: a plurality of magnetic tunnel junction elements arranged on a semiconductor substrate; and a plurality of selection transistors electrically connected to first ends of the plurality of magnetic tunnel junction elements. A plurality of first bit lines are respectively connected to the first ends of the magnetic tunnel junction elements via one or more of the selection transistors. A plurality of upper electrodes are respectively connected to second ends of the plurality of magnetic tunnel junction elements. A plurality of second bit lines are respectively connected to the second ends of the magnetic tunnel junction elements via the upper electrodes. The upper electrodes extend along the second bit lines, and one of the upper electrodes is commonly connected to the second ends of the plurality of magnetic tunnel junction elements arranged in an extending direction of the second bit lines.

主权项

1. A semiconductor memory device comprising:
a plurality of magnetic tunnel junction elements on a semiconductor substrate; a plurality of selection transistors electrically connected to first ends of the magnetic tunnel junction elements, respectively; a plurality of first bit lines connected to the first ends of the magnetic tunnel junction elements via one or more of the selection transistors, respectively; a plurality of upper electrodes respectively connected to second ends of the magnetic tunnel junction elements; a plurality of second bit lines respectively connected to the second ends of the magnetic tunnel junction elements via the upper electrodes; and a plurality of via contacts electrically connected between the upper electrodes and the second bit lines, wherein the upper electrodes extend along the second bit lines, and one of the upper electrodes is commonly connected to the second ends of the plurality of magnetic tunnel junction elements arranged in an extending direction of the second bit lines, and one of the upper electrodes is connected to one of the second bit lines via the plurality of via contacts.