发明名称 Multi-level charge storage transistors and associated methods
摘要 Methods of fabricating charge storage transistors are described, along with apparatus and systems that include them. In one such method, a pillar of epitaxial silicon is formed. At least first and second charge storage nodes (e.g., floating gates) are formed around the pillar of epitaxial silicon at different levels. A control gate is formed around each of the charge storage nodes. Additional embodiments are also described.
申请公布号 US8859349(B2) 申请公布日期 2014.10.14
申请号 US201313745452 申请日期 2013.01.18
申请人 Micron Technology, Inc. 发明人 Sandhu Gurtej S.;Ramaswamy Durai Vishak Nirmal
分类号 H01L21/8247;H01L21/8246;H01L27/115;H01L29/66;H01L27/088 主分类号 H01L21/8247
代理机构 Schwegman Lundberg & Woessner, P.A. 代理人 Schwegman Lundberg & Woessner, P.A.
主权项 1. A method comprising: forming a pillar of epitaxially grown semiconductor material on a doped area of a vertical transistor, the pillar comprising a memory cell that is coupled to the vertical transistor through the doped area; forming a charge storage node around the pillar; and forming a control gate around the charge storage node.
地址 Boise ID US