| 摘要 |
PROBLEM TO BE SOLVED: To provide a small-sized buffer circuit having low latency.SOLUTION: A buffer circuit includes: a register string 41; and a control circuit 42 that performs control so as to rearrange a plurality of received data items in a transfer order, store them in the register string, and output them as one transfer data item when they are all set. The control circuit controls the register string so as to store storage data of each register in a preceding-stage register when the register string outputs a plurality of received data items; determines a write register according to the transfer order when the register string stores new received data; and controls the register string so as to store storage data of the write register in a post-stage register of the write register and store the new received data in the write register. |
