发明名称 AUTOMATIC GENERATION OF TEST LAYOUTS FOR TESTING A DESIGN RULE CHECKING TOOL
摘要 A method of automatically generating a set of test layouts for testing a design rule checking tool is described. A layout is a point in a space of several coordinates (Q_1,..., Q_M), and the design rule comprises N design constraints (C_1,..., C_N) numbered 1 to N, wherein N is greater or equal two and each design constraint (C_K; K=1,...,N) is a boolean-valued function of one or more of the coordinates (Q_1,..., Q_M). The set of test layouts includes: one or more zero-error layouts (Q1); one or more one-error layouts (Q2); and one or more two-error layouts (Q3). A zero-error layout is a layout that satisfies all of the design constraints (C_1,..., C_N). A one-error layout is a layout that violates exactly one of the design constraints (C_1, C_2,..., C_N). A two-error layout is a layout that violates exactly two of the design constraints (C_1, C_2,..., C_N). Computer-executable instructions for instructing a computer to carry out the method may be stored on a data carrier.
申请公布号 WO2014163519(A1) 申请公布日期 2014.10.09
申请号 WO2013RU00272 申请日期 2013.04.01
申请人 FREESCALE SEMICONDUCTOR INC;SOTNIKOV, MIKHAIL ANATOLIEVICH;KERRE, ALEXANDER LEONIDOVICH 发明人 SOTNIKOV, MIKHAIL ANATOLIEVICH;KERRE, ALEXANDER LEONIDOVICH
分类号 G06F11/36;G06F17/50 主分类号 G06F11/36
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