发明名称 DE-CORRELATING TRAINING PATTERN SEQUENCES BETWEEN LANES IN HIGH-SPEED MULTI-LANE LINKS AND INTERCONNECTS
摘要 Methods, apparatus and systems for de-correlating training pattern sequences for high-speed links and interconnects. The high-speed links and interconnects employs multiple lanes in each direction for transmitting and receiving data, and may be physically implemented via signal paths in an inter-plane board such as a backplane or mid-plane, or via a cable. During link training, a training pattern comprising a pseudo random bit sequence (PBRS) is sent over each lane. The PBRS for each lane is generated by a PBRS generator based on a PRBS polynomial that is unique to that lane. Since each lane employs a different PRBS polynomial, the training patterns between lanes are substantially de-correlated. Link negotiation may be performed between link endpoints to ensure that the PBRS polynomials used for all of the lanes in the high-speed link or interconnect are unique. Exemplary uses include Ethernet links, Infiniband links, and multi-lane serial interconnects.
申请公布号 WO2014164004(A1) 申请公布日期 2014.10.09
申请号 WO2014US19805 申请日期 2014.03.03
申请人 INTEL CORPORATION;LUSTED, KENT C.;RAN, ADEE O. 发明人 LUSTED, KENT C.;RAN, ADEE O.
分类号 H04L29/02;H04L29/10 主分类号 H04L29/02
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