| 摘要 |
Systems and methods are disclosed including a duty cycle module having two timer circuits (113, 121) to measure pulse widths of a clock signal. Two comparators (134, 136) are used to generate control signals (UP, DOWN) depending upon comparisons of the pulse width measurements. In response to the control signals, either the clock signal or an inverted clock signal may be programmably delayed such that combination of the clock signal and the inverted clock signal results in a corrected clock signal. Systems and methods are also disclosed for verifying operation of a duty cycle module. |
