发明名称 |
JUNCTIONLESS NANOWIRE TRANSISTORS FOR 3D MONOLITHIC INTEGRATION OF CMOS INVERTERS |
摘要 |
The invention provides a three dimensional (3D) semi-conductor device comprising a first junctionless transistor doped with dopants of the same polarity; a second junctionless transistor doped with dopants of the same polarity; and the second junctionless transistor and the first junctionless transistor comprise an opposite dopant polarity are stacked in a vertical arrangement, where the first and second junctionless transistors are separated by an insulating layer. The invention makes use of the fact that the transistors are uniformly doped with the same polarity to provide a junctionless transistor. The junctionless concept provides that the junction is already formed, so there is no high temperature step associated with junction formation or junction regrowth. This is an important advantage in the junctionless concept in relation to 3D monolithic integration that allows for vertical stacking of the transistors to form a three dimensional CMOS inverter. |
申请公布号 |
WO2014162018(A1) |
申请公布日期 |
2014.10.09 |
申请号 |
WO2014EP56959 |
申请日期 |
2014.04.07 |
申请人 |
UNIVERSITY COLLEGE CORK - NATIONAL UNIVERSITY OF IRELAND, CORK |
发明人 |
HURLEY, PAUL;CHERKAOUI, KARIM;DJARA, VLADIMIR |
分类号 |
H01L21/8258;H01L21/8252;H01L27/06;H01L27/092 |
主分类号 |
H01L21/8258 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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