CLOCK GENERATING CIRCUIT HAVING PARASITIC OSCILLATION SUPPRESSING UNIT AND METHOD OF SUPPRESSING PARASITIC OSCILLATION USING THE SAME

摘要

Disclosed herein are a clock generating circuit having a parasitic oscillation suppressing unit and a method of suppressing parasitic oscillation using the same. An output VDD of a parasitic component eliminating circuit is maintained in a high or low state according to the condition in which the output VDD falls from the high state to the low state and the condition in which the output VDD rises from the low state to the high state based on a threshold voltage VSPH when an input signal of the parasitic component eliminating circuit is changed from 0 to 1 and a threshold voltage VSPL when the input signal of the parasitic component eliminating circuit is changed from 1 to 0. Undesired parasitic oscillation is eliminated (suppressed) by the parasitic component eliminating circuit provided between a oscillator and a buffer.

主权项

1. A clock generating circuit having a parasitic oscillation suppressing unit, comprising:
an oscillator receiving a driving signal for oscillation and oscillating a sine wave having a predetermined frequency; a first buffer receiving the sine wave output from the oscillator and outputting a square wave represented by 0 and 1; a second buffer receiving an output from the first buffer and outputting an opposite value to the received value; a crystal resonator connected in parallel with the oscillator, receiving a driving signal from the outside, resonated in a desired specific frequency band so as to generate a clock of an accurate time at a final output terminal, providing an input signal of the oscillator, and receiving an output signal fed back from the oscillator; and a parasitic component eliminating circuit installed between the oscillator and the first buffer in order to eliminate a parasitic component introduced between the oscillator and the first buffer.