发明名称 OPERATIONAL AMPLIFIER CIRCUIT
摘要 In aspects of the invention, an operational amplifier circuit includes: an N-MOS auxiliary current source connected in parallel to the N-MOS differential pair, the N-MOS auxiliary current source turning ON when the N-MOS differential pair turns OFF caused by a decreased common mode input voltage given to the pair of voltage input terminals, drawing a current from the active load for the P-MOS differential pair. Aspects of the invention also include a P-MOS auxiliary current source connected in parallel to the P-MOS differential pair, the P-MOS auxiliary current source turning ON when the P-MOS differential pair turns OFF caused by an increased common mode input voltage given to the pair of voltage input terminals, delivering a current to the active load for the-N-MOS differential pair.
申请公布号 US2014300414(A1) 申请公布日期 2014.10.09
申请号 US201414231810 申请日期 2014.04.01
申请人 FUJI ELECTRIC CO., LTD. 发明人 IWAMOTO Motomitsu
分类号 H03F3/45 主分类号 H03F3/45
代理机构 代理人
主权项 1. An operational amplifier circuit comprising: an N-MOS differential pair composed of a pair of N-channel type MOS-FETs connected to a pair of voltage input terminals; an active load for a P-MOS differential pair connected to the N-MOS differential pair and a current source for the N-MOS differential pair connected to the N-MOS differential pair; the P-MOS differential pair composed of a pair of P-channel type MOS-FETs connected to the pair of voltage input terminals; an active load for the N-MOS differential pair connected to the P-MOS differential pair and a current source for the P-MOS differential pair connected to the P-MOS differential pair; an N-MOS auxiliary current source composed of a pair of N-channel type MOS-FETs that are connected in parallel to the pair of N channel type MOS-FETs composing the N-MOS differential pair and have a gate biased at a voltage slightly higher than a voltage that turns OFF the pair of N-channel type MOS-FETs composing the N-MOS differential pair; and a P-MOS auxiliary current source composed of a pair of P-channel type MOS-FETs that are connected in parallel to the pair of P channel type MOS-FETs composing the P-MOS differential pair and have a gate biased at a voltage slightly lower than a voltage that turns OFF the pair of P-channel type MOS-FETs composing the P-MOS differential pair.
地址 Kawasaki-shi JP