TWO-STEP INTERCONNECT TESTING OF SEMICONDUCTOR DIES

摘要

The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.

主权项

1. A method of testing an interconnect in a semiconductor die, comprising:
providing the semiconductor die, wherein the semiconductor die comprises:
a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die,at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, andan electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element; testing a first signal path in the semiconductor die for manufacturing defects, the first signal path comprising a first part of the interconnect-under-test and a first deviation path from the interconnect-under-test over the electrical component to a third electrical contact element, thus obtaining first test results; and testing a second signal path in the semiconductor die for manufacturing defects, the second signal path comprising a second part of the interconnect-under-test and a second deviation path from the interconnect-under-test over the electrical component to a third electrical contact element, thus obtaining second test results, wherein the interconnect-under-test comprises the first part and the second part of the interconnect-under-test.