发明名称 |
DIGITAL PERIOD DIVIDER |
摘要 |
<p>A digital period divider has a first counter with R least significant bits (LSB) and P most significant bits (MSB) having a count input and a reset input, wherein the count input receives a first clock signal and the reset input receives a second clock signal; a latch having P bits and being coupled with the P bits of the first counter; a second counter having P bits and a count input and a reset input, wherein the count input receives the first clock signal; and a first comparator operable to compare the P bits of the latch with the P bits of the second counter and generating an output signal, wherein the output signal is also fed to the reset input of the second counter.</p> |
申请公布号 |
WO2014164376(A1) |
申请公布日期 |
2014.10.09 |
申请号 |
WO2014US22188 |
申请日期 |
2014.03.08 |
申请人 |
MICROCHIP TECHNOLOGY INCORPORATED |
发明人 |
JULICHER, JOSEPH;KILZER, KEVIN;VAN EEDEN, COBUS |
分类号 |
G01P3/487;H02P6/16;H03K21/38 |
主分类号 |
G01P3/487 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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