发明名称
摘要 <p>A signal multiplexing device includes a selector (1) that selects one of input data (4) and a complementary signal (16), a clock recovery circuit (30a) that adjusts the phase of a recovered clock (7) to the timing of the output signal of the selector (1), and a flip-flop circuit (3) that performs identification/recovery of the output signal of the selector (1) based on the recovered clock (7). The frequency of the complementary signal (16) is an integral submultiple of the frequency of the recovered clock (7). The selector (1) selects the complementary signal (16) during part of the no-signal period of the input data (4).</p>
申请公布号 JP5603441(B2) 申请公布日期 2014.10.08
申请号 JP20120555791 申请日期 2012.01.20
申请人 发明人
分类号 H04L7/033;H03K5/00;H03L7/08 主分类号 H04L7/033
代理机构 代理人
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