| 发明名称 |
Memory devices, architectures and methods for memory elements having dynamic change in property |
| 摘要 |
A memory device can include at least one array comprising a plurality of elements programmable between at least two different states, each state having a different time to a change in property under applied sense conditions; a read circuit configured to apply the sense conditions to selected elements and detect changes in property of the selected elements to generate read data; a latch circuit configured to store read data from the read circuit; and a transfer path configured to provide a parallel data transfer path between the read circuit and the latch circuit. |
| 申请公布号 |
US8854873(B1) |
申请公布日期 |
2014.10.07 |
| 申请号 |
US201213464926 |
申请日期 |
2012.05.04 |
| 申请人 |
Adesto Technologies Corporation |
发明人 |
Hollmer Shane Charles;Dinh John;Lewis Derric Jawaher Herman |
| 分类号 |
G11C11/4091 |
主分类号 |
G11C11/4091 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory device, comprising:
at least one array comprising a plurality of elements programmable between at least two different states, each state having a different time to a change in property under applied sense conditions; a read circuit configured to apply the sense conditions to selected elements and detect changes in property in the selected elements to generate read data; a latch circuit configured to store read data from the read circuit; and a transfer path configured to provide a parallel data transfer path between the read circuit and the latch circuit. |
| 地址 |
Sunnyvale CA US |
