| 摘要 |
A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s. |
| 主权项 |
1. A non-volatile memory bitcell comprising:
a first active region in a substrate, the first active region comprising a source, a drain, and a well, the source having a first implant of a first conductivity type, the drain having a second implant of a second conductivity type of opposite polarity to the first conductivity type, the well having the second conductivity type; a second active region in the substrate separated from the first active region by a nonconductive region; a floating gate extending above the substrate from a portion of the first active region between the source and the drain to a portion of the second active region over the nonconductive region, the floating gate not extending over to active regions other than the first and second active regions; and a capacitor comprising a first plate and a second plate, the first plate comprising a portion of the floating gate above the second active region, and the second plate comprising a portion of the second active region underneath the floating gate. |
