Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains

摘要

A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.

主权项

1. A semiconductor apparatus, comprising:
an arrangement of semiconductor devices located on a surface of semiconductor material, where each semiconductor device in the arrangement of semiconductor devices is associated with a first power domain; at least one voltage pathway defined on the surface of the semiconductor material that divides the arrangement of semiconductor devices into one or more groups, where the at least one voltage pathway comprises one or more areas reserved on the surface for placement of one or more circuits associated with a second power domain that is different than the first power domain; and one or more deposited networks of conductive material configured to electrically connect at least one circuit element to at least one other circuit element, the at least one circuit element located in a first voltage pathway of the at least one voltage pathway and the at least one other circuit element located in a second voltage pathway in the at least one voltage pathway.