| 摘要 |
An apparatus and method for controlling a memory are disclosed. A control clock generation unit generates at least one control clock transmitted together when data is transmitted to and received from a memory. A memory interface unit writes the data in the memory or reads the data from the memory. A memory control unit detects an estimated time when specific data is read by comparing the specific data with data read at each estimated time, with respect to at least one estimated time preset to read the specific data in correspondence with the control clock when reading the preset specific data from the memory. A system initialization unit computes a delay time delayed in reading the specific time by comparing the detected estimated time with time when the specific data is transmitted from the memory, and reads data at an optimum time obtained by adding the computed delay time to the time when the data is transmitted from the memory. According to the present invention, a communication delay between a controller and the memory is solved by newly setting a delay time during initialization even when configuring a new system in a PCB. The present invention can also be used in a high speed SRAM, DRAM, and flash memory, and realized by minimum additional logic by utilizing an internal clock and register. [Reference numerals] (110) Control clock generation unit; (120) Memory interface unit; (130) Memory control unit; (140) System initialization unit |
