发明名称 Nonvolatile memory unit with secure erasing function
摘要 An apparatus includes a nonvolatile memory, an interface that at least receives an erase command of the nonvolatile memory, a first controller that controls the nonvolatile memory to execute data erasing on the basis of the erase command output from the interface, an external input unit which is installed independently of the interface, a second controller that controls the nonvolatile memory to execute data erasing on the basis of an erase instruction signal output from the external input unit, and a change-over circuit that switches between connection of the first controller with the nonvolatile memory and connection of the second controller with the nonvolatile memory, wherein the second controller controls the nonvolatile memory to execute data erasing on the basis of the erase instruction when the connection of the second controller with the nonvolatile memory is established by the change-over circuit.
申请公布号 US8856474(B2) 申请公布日期 2014.10.07
申请号 US201113224710 申请日期 2011.09.02
申请人 Fujitsu Limited 发明人 Ise Masahiro;Garbe Michiyo;Abe Jin
分类号 G06F12/00;G11C16/30;G11C16/16;G06F12/02 主分类号 G06F12/00
代理机构 Staas & Halsey LLP 代理人 Staas & Halsey LLP
主权项 1. A nonvolatile memory unit comprising: a nonvolatile memory; an interface that at least receives an erase command signal for the nonvolatile memory; a first controller that controls to access the nonvolatile memory, and to erase, based on the erase command signal output from the interface, data stored in the nonvolatile memory; an external input unit which is arranged independently of the interface; a second controller that controls to erase, based on an erase instruction signal output from the external input unit, data stored in the nonvolatile memory; and a change-over circuit that switches between connection of the first controller with the nonvolatile memory and connection of the second controller with the nonvolatile memory, wherein the second controller controls to erase the data in accordance with the erase instruction signal independently of the first controller when one of the first controller and the interface enters one of a disabled state and a state in which reception of the erase command signal is not allowed.
地址 Kawasaki JP