| 发明名称 |
System for I-Q phase mismatch detection and correction |
| 摘要 |
System for I-Q phase mismatch detection and correction. An apparatus to correct a phase mismatch between I and Q signals includes a correction circuit configured to continuously compare a reference signal and a phase error signal associated with the I and Q signals to generate an I bias signal and a Q bias signal, a first CMOS buffer configured to receive the I signal and the I bias signal and output a phase adjusted I signal based on the I bias signal, and a second CMOS buffer configured to receive the Q signal and the Q bias signal and output a phase adjusted Q signal based on the Q bias signal. |
| 申请公布号 |
US8854098(B2) |
申请公布日期 |
2014.10.07 |
| 申请号 |
US201113011716 |
申请日期 |
2011.01.21 |
| 申请人 |
QUALCOMM Incorporated |
发明人 |
Yang Jeongsik;Park Chan Hong;Lee Sang-oh |
| 分类号 |
H03H11/16;H03D7/14;H03D7/16;H03L7/081;H04L27/36;H04L27/38 |
主分类号 |
H03H11/16 |
| 代理机构 |
|
代理人 |
Mobarhan Ramin |
| 主权项 |
1. An apparatus to correct a phase mismatch between I and Q signals, the apparatus comprising:
a correction circuit configured to continuously compare a reference signal and a phase error signal associated with the I and Q signals to generate an I bias signal and a Q bias signal; a first CMOS buffer configured to receive the I signal and the I bias signal and output a phase adjusted I signal based on the I bias signal; and a second CMOS buffer configured to receive the Q signal and the Q bias signal and output a phase adjusted Q signal based on the Q bias signal. |
| 地址 |
San Diego CA US |
